K20 EVM - Kinetis Cortex-M4 K20 UART 테스트
K20의 UART는 일반 UART 3채널로 구성되어 있다.
PTA1 -> UART0_RX
PTA2 -> UART0_TX
PTB16 ->UART0_RX
PTB17 ->UART0_TX
PTD6 -> UART0_RX
PTD7 -> UART0_TX
PTC3 ->UART1_RX
PTC4 ->UART1_TX
PTD2 ->UART2_RX
PTD3 ->UART2_TX
UART clocking
UART0 and UART1 modules operate from the core/system clock, which provides higher
performance level for these modules. All other UART modules operate from the bus
clock.
K20 UART 초기화 함수
// Serial Prot0 Utility Fuction Routine
void U0_Init(unsigned char baud)
{
//UART포트 설정
// Enable the UART_RXD function on PTA1
PORTA_PCR1 = PORT_PCR_MUX(0x2);
// Enable the UART_TXD function on PTA2
PORTA_PCR2 = PORT_PCR_MUX(0x2);
//UART0 클럭 Enable
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
//UART disable
UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
//Configure the UART for 8-bit mode, no parity(디폴트 값 사용)
UART_C1_REG(UART0_BASE_PTR) = 0;
U0_SetBaud(baud);
//Enable UART
UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
}
UARTx_S1(UART Status Register 1)
DRE
Transmit Data Register Empty Flag
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is
not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data
register (D). For more efficient interrupt servicing, all data except the final value to be written to the buffer
must be written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the
clearing of the TRDE flag. This is more efficient because the TDRE reasserts until the watermark has
been exceeded. So, attempting to clear the TDRE with every write will be ineffective until sufficient data
has been written.
0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
1 The amount of data in the transmit buffer is less than or equal to the value indicated by
TWFIFO[TXWATER] at some point in time since the flag has been cleared.
5
RDRF
Receive Data Register Full Flag
RDRF is set when the number of datawords in the receive buffer is equal to or more than the number
indicated by RWFIFO[RXWATER]. A dataword that is in the process of being received is not included in
the count. RDRF is prevented from setting while S2[LBKDE] is set. Additionally, when S2[LBKDE] is set,
the received datawords are stored in the receive buffer but over-write each other. To clear RDRF, read S1
when RDRF is set and then read D. For more efficient interrupt and DMA operation, read all data except
the final value from the buffer, using D/C3[T8]/ED. Then read S1 and the final data value, resulting in the
clearing of the RDRF flag. Even if RDRF is set, data will continue to be received until an overrun condition
occurs.
0 The number of datawords in the receive buffer is less than the number indicated by RXWATER.
1 The number of datawords in the receive buffer is equal to or greater
K20 UART 송수신 함수
unsigned char U0_GetByte(void)
{
//데이터가 수신되면
while (!(UART_S1_REG(UART0_BASE_PTR) & UART_S1_RDRF_MASK));
//데이터 읽어옴
return UART_D_REG(UART0_BASE_PTR);
}
void U0_PutByte(unsigned char Data)
{
//송신 FIFO가 비어지면
while(!(UART_S1_REG(UART0_BASE_PTR) & UART_S1_TDRE_MASK));
//데이터 전송
UART_D_REG(UART0_BASE_PTR) = Data;
}
