Introduction
The goal of this project is to download a project build
under the IAR tools using Flash methods to IAR Flash Tools
Use the IAR 4.30A
Flash feature
The IAR Embedded Workbench IDE features a Tools Flash
utility.
This method can write in flash a IAR file format (*.sim)
(output format generated using option simple-code)
The IAR Flash download option to use a flash loader to
download your application to flash memory. If a flash loader is available
for the selected chip, it will be used as default. A flash loader can be
described as being an agent that is downloaded to the target. It fetches
the actual application from the C-SPY debugger and programs it into flash
memory.
The flash loader uses the file I/O mechanism to read the
application program from the host. When the Flash download option is
enabled, the following steps will be performed when the debug session
starts:
1 C-SPY downloads the flash loader into target RAM.
2 C-SPY starts execution of the flash loader.
3 The flash loader opens the file holding the application
code.
4 The flash loader reads the application code and programs
it into flash memory.
5 The flash loader terminates.
6 C-SPY switches context to the user application.
A set of flash loaders for various micro controllers is
provided with the ARM IAR Embedded Workbench. In addition to these, other
flash loaders are provided by chip manufacturers and third-party vendors.
Two output files must be generated. The first is the usual
UBROF file (d79) that provides the debugger with debug and symbol
information. The second file is an IAR file (*.sim) that will be opened and
read by the flash loader when downloading the application to flash memory.
To create the extra output file, choose Project->Options
and select the linker category. Select the Allow C-SPY-specific extra
output file option. In the Extra Output dialog, select the Generate extra
output file option. Choose intel-extended output format and format variant
None. Do not override the default output file.
Any errors during the download will be logged to a log
file. The log file will have the same path and name as the output files but
with the tail and filename extension _flash.log.
Process
- Compile
the Flash Debug workspace application to generate the IAR file named
basic.sim and the debug file named basic.d79
1) Download
this application using a JTAG ICE interface with the "Debug"
command
2)
Open the “Debug Log” window
Trace:
in Debug Log
Loaded
macro file:
E:\compil\iar_EVAL\IAR4.30A_last\arm\config\flashloader\Atmel\FlashAT91SAM7X.mac
J-Link firmware: V1.20 (J-Link
compiled Aug 19 2005 19:37:55 ARM Rev.5)
JTAG speed is initially set to: 32
kHz
Halting CPU core
Initial reset was performed
J-Link found 1 JTAG device. ARM core
Id: 3F0F0F0F(ARM7)
Device at TAP0 selected
**** Warning: Chip has already been
halted.
---------------------------------------- FLASH Download V1.2
---------------------------------------- 08/September/2005
Resetting Target using RESET pin
Set Main Oscillator
Set PLL to 96MHz
Set Master Clock to 48MHz
---------------------------------------- GPNVM 2 is already Set
Changing mapping: RAM mapped to 0
---------------------------------------- Chip ID 0x271B0940
---------------------------------------- Extention 0x00000000
---------------------------------------- Flash Version 0x00000112
Auto JTAG speed: 4000 kHz
4827 bytes downloaded (11.61
Kbytes/sec)
Loaded debugee:
E:\compil\iar_EVAL\IAR4.30A_last\arm\config\flashloader\Atmel\FlashAT91SAM7X.d79
Target reset
execUserFlashReset()
Downloader Version 1.2 08-SEP-2005
Download1: AT91SAM7X At: 0x100000
Download: AT91SAM7X Version: 0x112
Download:page 0
Download:page 1
Download:page 2
Download:page 3
Program exit reached.
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