| xc3_evm Project Status (08/29/2010 - 22:49:41) | |||
| Project File: | xc3_evm.ise | Current State: | Programming File Generated |
| Module Name: | BoardTest |
|
No Errors |
| Target Device: | xc3s100e-5tq144 |
|
1 Warning |
| Product Version: | ISE 10.1.03 - WebPACK |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
| xc3_evm Partition Summary | [-] | |||
| No partition information was found. | ||||
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 27 | 1,920 | 1% | ||
| Number of 4 input LUTs | 30 | 1,920 | 1% | ||
| Logic Distribution | |||||
| Number of occupied Slices | 27 | 960 | 2% | ||
| Number of Slices containing only related logic | 27 | 27 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 27 | 0% | ||
| Total Number of 4 input LUTs | 47 | 1,920 | 2% | ||
| Number used as logic | 30 | ||||
| Number used as a route-thru | 17 | ||||
| Number of bonded IOBs | |||||
| Number of bonded | 10 | 108 | 9% | ||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 老 8 29 22:48:17 2010 | 0 | 0 | 2 Infos | |
| Translation Report | Current | 老 8 29 22:48:28 2010 | 0 | 0 | 0 | |
| Map Report | Current | 老 8 29 22:48:39 2010 | 0 | 0 | 2 Infos | |
| Place and Route Report | Current | 老 8 29 22:48:55 2010 | 0 | 1 Warning | 2 Infos | |
| Static Timing Report | Current | 老 8 29 22:49:03 2010 | 0 | 0 | 3 Infos | |
| Bitgen Report | Current | 老 8 29 22:49:39 2010 | 0 | 0 | 0 | |